1. Field of the Invention
Example embodiments of the present invention relate generally to semiconductor devices and related methods of manufacture. More particularly, example embodiments of the present invention relate to a semiconductor device having a simplified structure adapted to improve its electrical characteristics, and a related method of manufacture.
A claim of priority is made to Korean Patent Application No. 2005-33872, filed on Apr. 25, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Volatile semiconductor memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM) lose stored data when their power is turned off, whereas nonvolatile semiconductor memory devices such as erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), or a flash memory can maintain stored data even when their power is turned off. Because volatile semiconductor memory devices lose data when they lose power, they are not very attractive for certain applications such as long term storage in portable devices. On the other hand, nonvolatile semiconductor memory devices also have limitations such as their relatively low degree of integration, relatively slow response time, and high operating voltage. To address at least some of the limitations of nonvolatile memory devices, ferroelectric random access memories (FRAMs) have been developed.
A FRAM is a nonvolatile memory device that stores data using double polarization of a ferroelectric material. Constructionally, a FRAM contains an array of ferroelectric capacitors, which use the ferroelectric material as a dielectric. The ferroelectric material forms a nonlinear dielectric having a dielectric polarization that forms a hysteresis loop based on variations of an electric field. FRAM devices tend to a have rapid operating speed, a low operating voltage, and high durability. As a result, FRAM devices are considered an attractive option for next generation memory systems. At present, ferroelectric materials such as PZT[(Pb, Zr)TiO3], SBT (SrBi2Ta2O9) and BLT [(Bi, La)TiO3] have been developed for FRAM devices.
A FRAM device is disclosed, for example, in Korean Laid-Open Patent Publication No. 1997-77662, U.S. Pat. No. 6,366,489, and Japanese Laid-Open Patent Publication No. 2003-243621.
FIGS. 1 to 4 are cross-sectional views illustrating various methods of manufacturing a conventional ferroelectric memory device.
Referring to FIG. 1, an isolation layer 3 is formed in an upper portion of a semiconductor substrate 1 to divide semiconductor substrate 1 into a cell area “C”, a first peripheral circuit area “P1” and a second peripheral circuit area “P2”.
A gate oxide layer is formed on a portion of the semiconductor substrate 1 that is exposed through isolation layer 3, and then the gate oxide layer is partially etched to form first gate oxide layer patterns 6 in cell area C and a second gate oxide layer pattern 6′ in first peripheral circuit area P1.
A first gate conductive layer pattern 9, a second gate conductive layer pattern 12, and a first gate mask pattern 15 are successively formed on first gate oxide layer patterns 6 in cell area C. At the same time, a third gate conductive layer pattern 9′, a fourth gate conductive layer pattern 12′ and a second gate mask pattern 15′ are successively formed on second gate oxide layer pattern 6′ in first peripheral circuit area P1. A fifth gate conductive layer pattern 9″, a sixth gate conductive layer pattern 12″ and a third gate mask pattern 15″ are formed on isolation layer 3 in first peripheral circuit area P1 without a gate oxide layer pattern between isolation layer 3 and the fifth gate conductive layer pattern 9″. As a result, first gate structures 21 are formed in the cell area C, and second and third gate structures 21′ and 21″ are formed in first peripheral circuit area P1.
Respective first, second and third gate spacers 18, 18′ and 18″ are formed on sidewalls of respective first, second and third gate structures 21, 21′ and 21″, and then source/drain regions 24 and 27 are formed in semiconductor substrate 1 in cell area C by an ion implantation process using first gate structures 21 in cell area C as a mask.
After a first conductive layer is formed on semiconductor substrate 1 to cover first gate structures 21 in cell area C, the first conductive layer is patterned to form pads 30 and 33 in contact with source/drain regions 24 and 27, respectively.
Referring to FIG. 2, a first insulating interlayer 36 is formed on an overall upper face of the semiconductor substrate 1 to cover cell area C, first peripheral circuit area P1 and second peripheral circuit area P2, and then a second insulating interlayer 39 is formed on first insulating interlayer 36.
Second insulating interlayer 39 and first insulating interlayer 36 are partially etched by a photolithography process to form a first contact hole 45 in cell area C, second, third, fourth, fifth and sixth contact holes 48, 51, 54, 57 and 60 in first peripheral circuit area P1, and a seventh contact hole 42 in second peripheral circuit area P2. First contact hole 45 in cell area C exposes pad 33; third contact hole 51 in the first peripheral circuit area P1 exposes fourth gate conductive layer pattern 12′ of second gate structure 21′; and fifth contact hole 57 exposes sixth gate conductive layer pattern 12″ of third gate structure 21″. Second contact hole 48, fourth contact hole 54 and sixth contact hole 60 expose semiconductor substrate 1 in first peripheral circuit area P1. Seventh contact hole 42 exposes semiconductor substrate 1 in second peripheral circuit area P2. Here, openings for each forming a bit line are formed at an upper portion of first, second, fourth, fifth and seventh contact holes 42, 48, 54, 57 and 42.
Referring to FIG. 3, a second conductive layer is formed on second insulating interlayer 39 to fill first through seventh contact holes 45, 48, 51, 54, 57, 60 and 42, and then an upper portion of the second conductive layer is removed until second insulating interlayer 39 is exposed. As a result, a first bit line 66′ and a first contact 69 are formed in first contact hole 45 of cell area C, and a second bit line 66″ and a second contact 72 are formed in second contact hole 48 of first peripheral circuit area P1. A third contact 75 is formed in third contact hole 51 of first peripheral circuit area P1, and a third bit line 66′″ and a fourth contact 78 are formed in fourth contact hole 54. A fourth bit line 66″″ and a fifth contact 81 are formed in fifth contact hole 57 of first peripheral circuit area P1, and a sixth contact 84 is formed in sixth contact hole 60. A fifth bit line 66 and a seventh contact 63 are formed in seventh contact hole 42 of second peripheral circuit area P2.
Referring to FIG. 4, a third insulating interlayer 87 is formed on first through fifth bit lines 66′, 66″, 66′″, 66″″ and 66, third and sixth contacts 75 and 84 and second insulating interlayer 39.
Third insulating interlayer 87, second insulating interlayer 39 and first insulating interlayer 36 are successively etched to form eighth contact holes exposing pads 30, which make contact with source/drain regions 24. A third conductive layer is formed on third insulating interlayer 87 to fill up eighth contact holes, and then the third conductive layer formed on third insulating interlayer 87 is removed to form eighth contacts 90 in the eighth contact holes. Eighth contacts 90 make contact with pads 30, which are respectively positioned on source/drain regions 24.
In the method described with reference to FIGS. 1 through 4, the semiconductor substrate and the pads or gate structures may be damaged in an etching process used to form the contact holes through the insulating interlayers, because the contact holes have substantially different depths from one another. As illustrated in FIG. 2, where insulating interlayers 36 and 39 are etched to form contact holes 42, 45, 48, 51, 54, 57 and 60, which have substantially different depths from each other, a portion of semiconductor substrate 1 exposed in the peripheral circuit area, or gate structures 21′ and 21″ are damaged in the etching process. Furthermore, as illustrated in FIG. 4, where insulating interlayers 36, 39 and 87 are etched to form the contact holes, pads 30 on source/drain regions 24 positioned in cell area C are commonly damaged, thereby deteriorating the electrical characteristics of the semiconductor device.
After pads 30 and 33 are formed on source/drain regions 24 and 27, a number of processes are generally further performed, which complicates the structure, and increases the manufacturing process time and cost of the semiconductor device. In general, more than 40 processes are typically performed to form pads 30 and 33, and therefore enormous time and cost are needed to form pads 30 and 33. Accordingly, a simplified structure for the nonvolatile memory device shown in FIGS. 1 through 4 may be useful for decreasing the manufacturing costs, increasing the level of integration, and enhancing the electrical characteristics of the devices.